Freescale Semiconductor /MK70F15 /DDR /CR28

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Interpret as CR28

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CSMAP)CSMAP 0 (0)REDUC 0 (0)BIGEND 0 (0)CMDLATR

REDUC=0, CMDLATR=0, BIGEND=0

Description

DDR Control Register 28

Fields

CSMAP

Chip Select Map

REDUC

Controls the width of the memory datapath

0 (0): 16-bit - standard operation using full memory bus

1 (1): 8-bit - Memory datapath width is half of the maximum size. The upper half of the memory busses (DQ, DQS, and DM) are unused and relevant data only exists in the lower half of the busses.

BIGEND

Big Endian Enable

0 (0): Little endian

1 (1): Big endian

CMDLATR

Command Latency Reduction Enable

0 (0): Disable

1 (1): Enable

Links

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